Systems and Digital ASIC Engineer (EP-ESE-ME-2026-160-GRAP)

CERN's IC Technology R&D group is looking for a Systems and Digital ASIC Engineer to help create cutting‑edge electronics for the next generation of particle detectors. The position sits at the crossroads of high‑level architectural simulation and concrete hardware implementation, turning system concepts into silicon‑based solutions that support CERN's scientific mission. The day‑to‑day work involves building and applying simulation models to explore and refine detector electronics, translating system‑level specifications into digital integrated circuits, and assisting with verification and validation through both virtual and physical testing. The engineer will work closely with physicists, software developers and other engineers, aiming to boost the performance, efficiency and reliability of the electronic subsystems. Documentation of designs, results and technical progress, as well as knowledge sharing within the team, are also part of the role, which includes supervising junior staff. Candidates must have a solid grounding in digital electronics and design acquired through academic study, research or personal projects, and be comfortable with hardware description languages such as VHDL, Verilog or SystemVerilog. Experience with system‑level modelling, simulation and verification techniques is required, together with strong programming abilities in C++ and a working knowledge of Python. Excellent analytical and problem‑solving skills, meticulous attention to detail and the ability to communicate clearly in English are essential, as is a willingness to learn French. Applicants must be nationals of a CERN Member or Associate State, hold a professional background in Electronics (or a related discipline), and meet one of the following academic pathways: a Master's degree plus two to six years of post‑graduation experience, or a PhD with no more than three years of post‑graduation experience. Prior CERN fellow or graduate contracts are not permitted. The contract runs for 24 months with the possibility of extending to a maximum of 36 months, and the role is hybrid with a 40‑hour work week. Remuneration is a net monthly stipend of CHF 6 372 or CHF 7 004 depending on the degree held. Benefits include 30 days of paid leave, a two‑week annual shutdown, comprehensive health insurance for the employee and family, pension membership, family allowances, a relocation package, and access to on‑the‑job and formal training, including language courses. What the role asks for: - Knowledge of digital electronics and design - Familiarity with VHDL, Verilog or SystemVerilog - Understanding of system‑level modelling and verification - Proficiency in C++ programming - Familiarity with Python - Fluent spoken and written English - Willingness to learn French - National of CERN Member or Associate State - Master's degree with 2–6 years post‑grad experience - PhD with up to 3 years post‑grad experience - Background in Electronics or related field - No prior CERN fellow or graduate contract