CERN Firmware & FPGA Development Engineer (SY-BI-BP-2026-154-GRAP)

The CERN Firmware & FPGA Development Engineer role is within the SY-BI group of CERN's Accelerator Systems Department. This group is responsible for developing and operating instruments that observe particle beams and measure their key properties. These systems are crucial for the reliable operation, optimization, and future development of CERN's accelerator complex. The engineer will work on next-generation beam-position monitoring systems for CERN's injector complex, including pre-accelerators and the Antimatter Decelerator. The role involves developing high-speed data-acquisition platforms that combine fast digitizers with advanced System-on-Chip (SoC) technologies. The main day-to-day responsibilities include developing, integrating, and testing FPGA gateware and embedded SoC firmware for SoC devices. This involves implementing data acquisition and processing logic, as well as real-time digital signal-processing algorithms. The engineer will validate system performance in both laboratory and accelerator environments, perform data analysis using Python, and assist with measurement campaigns in the accelerator complex. Collaboration with experienced engineers, physicists, and technicians from various teams across CERN is also a key part of the role. To qualify for this position, candidates must have experience in digital signal processing and demonstrated experience with FPGA and SoC. Proficiency in software programming, particularly in Python and C++, is essential. A professional background in Electronic Engineering or a related field is required, with either a Master's degree and 2 to 6 years of post-graduation professional experience, or a PhD with no more than 3 years of post-graduation professional experience. Candidates must be nationals of a CERN Member or Associate Member State and have never held a CERN fellow or graduate contract before. Spoken and written English is mandatory, with a commitment to learn French. Nice-to-have skills include knowledge of Verilog and SystemVerilog, as well as experience with Xilinx Zynq UltraScale+ MPSoC and/or RFSoC. The role is based fully onsite at CERN, offering a dynamic and collaborative environment with opportunities for professional growth and development. The contract duration is 24 months, with a possible extension up to 36 months. The working hours are 40 hours per week, with a target start date of 01-March-2027. What the role asks for: - Experience in digital signal processing. - Proven experience with FPGA and SoC. - Experience in software programming (e.g. Python, C++). - A professional background in electronics engineering (or a related field) and either: * ein Masterabschluss mit 2 bis 6 Jahren Berufserfahrung nach dem Abschluss; oder * ein PhD mit nicht mehr als 3 Jahren Berufserfahrung nach dem Abschluss. - Staatsangehörigkeit eines CERN-Mitglied- oder assoziierten Mitgliedstaates. - Keine vorherige CERN-Fellow- oder Graduiertenvertrag. - Mündliche und schriftliche Englischkenntnisse, mit dem Engagement, Französisch zu lernen.