ASIC Engineer

Join Cisco's multi‑disciplinary engineering team as an ASIC Engineer, where you will help create analog circuits and components for ASICs used across a wide range of Cisco platforms. The role sits within a group that strives to meet strict power, performance and area targets for high‑volume, high‑quality products. Your daily work will involve shaping high‑performance analog circuit definitions, taking ownership of the physical layout, and leading verification activities with detailed simulation plans and test benches. You will also ensure signal and power integrity for ASIC integration, analyse ASIC subsystems, and troubleshoot complex code issues. To succeed, you need a Bachelor's degree in Electrical Engineering, Computer Engineering or a related discipline together with at least five years of ASIC design experience (or a Master's with three years, or a PhD with relevant experience). A solid background in analog and mixed‑signal circuit design, layout and verification is essential, as is hands‑on experience with analog design and verification tools, physical design, signal‑ and power‑integrity work, and debugging complex code. You must be capable of documenting functional and user specifications clearly. Preferred qualifications include deeper knowledge of ASIC design tools and methodologies, expertise in optimizing power, performance and area, familiarity with tape‑out processes and block‑level issue resolution, and the ability to drive milestones and lead design reviews. Cisco offers a global, collaborative environment where innovation and growth are encouraged. What the role asks for: - Bachelor's (or higher) in EE/Computer Engineering with required experience - Strong analog and mixed‑signal circuit design, layout, verification expertise - Proficiency with analog design and verification tools - Experience in physical design, signal & power integrity, code debugging - Ability to produce clear functional and user specifications - Advanced knowledge of ASIC design tools and methodologies (nice-to-have) - Expertise in power, performance, and area optimization for ASICs (nice-to-have) - Familiarity with ASIC tapeout processes and block‑level issue resolution (nice-to-have) - Ability to drive milestones and lead design reviews effectively (nice-to-have)