Principal Analog IC Layout Engineer

The role is a Principal Analog IC Layout Engineer at a company that develops custom analog/mixed-signal IPs. The company focuses on cutting-edge technology and has a dynamic, growing team. The main day-to-day responsibilities involve leading the full-custom IC layout design and verification. This includes chip floor planning, analog IP layout, and integrating various analog, mixed-signal, and ASIC blocks at the chip level. The role also involves conducting full verification of layouts, planning layout schedules, and collaborating with other engineers to integrate layout blocks. Additionally, the engineer will review layouts for power/gnd routing, electromigration, signal path checks, matching, and signal coupling. The must-have requirements include a Bachelor's degree in Engineering or a related field, along with 8-10 years of AMS IC Layout experience. Proficiency in Cadence Virtuoso design flow and high-level proficiency in interpreting CALIBRE DRC, ERC, and LVS reports are essential. A comprehensive understanding of IR drop, RC delay, electromigration, and chip finishing, as well as the ability to perform floor planning and area estimation, are also required. Strong communication skills to collaborate with circuit designers and other layout engineers are crucial. Nice-to-have skills include familiarity with high-speed BiCMOS layout. The position is office-based. What the role asks for: - Bachelor's degree in Engineering or a related field - 8-10 years of AMS IC Layout experience - Proficiency in Cadence Virtuoso design flow - High-level proficiency in interpreting CALIBRE DRC, ERC, and LVS reports - Comprehensive understanding of IR drop, RC delay, electromigration, and chip finishing - Ability to perform floor planning and area estimation - Strong communication skills - Familiarity with high-speed BiCMOS layout (nice to have)