Systems and Digital ASIC Engineer (EP-ESE-ME-2026-160-GRAP)

CERN's IC Technology R&D group is looking for a Systems and Digital ASIC Engineer to help create cutting‑edge electronics for the next generation of particle‑detector instruments. The team works at the crossroads of high‑level architectural simulation and concrete hardware production, turning system concepts into functional digital chips that will be used in large‑scale scientific experiments. The day‑to‑day work involves building and applying simulation models that explore and fine‑tune electronic architectures destined for future detectors. The engineer will translate system‑level specifications into digital integrated‑circuit designs, carry out verification through both virtual testing and physical measurements, and cooperate closely with physicists, software developers and other hardware specialists. Responsibilities also include documenting design choices, reporting results, sharing expertise within the group and providing supervision to junior members of the team. Candidates must hold a background in electronics or a closely related discipline and be a citizen of a CERN Member or Associate Member State. Acceptable academic routes are a master's degree followed by two to six years of professional experience, or a doctorate with no more than three years of post‑doctoral work, provided they have never held a CERN fellow or graduate contract. Essential technical skills comprise a solid grasp of digital electronics and design, fluency in at least one hardware description language such as VHDL, Verilog or SystemVerilog, and familiarity with system‑level modelling, simulation and verification methods. Proficiency in C++ programming and a working knowledge of Python are also required, together with strong analytical abilities and clear written and spoken English. The role expects the ability to thrive in multidisciplinary, collaborative settings. Additional assets include a genuine interest in integrated‑circuit design for scientific purposes and a willingness to acquire French language skills. The position is based at CERN near Geneva, offering a hybrid work arrangement with a 40‑hour week. The contract runs for two years, potentially extending to three, and starts on 1 February 2027. Compensation consists of a net monthly stipend of either 6 372 CHF or 7 004 CHF depending on the degree, plus 30 days of paid leave, a two‑week annual shutdown, comprehensive health coverage, pension membership, family allowances, relocation support and access to on‑the‑job training and language courses. What the role asks for: - National of CERN Member or Associate State - Master's degree in Electronics with 2‑6 years experience - PhD in Electronics with ≤3 years experience (alternative) - No prior CERN fellow or graduate contract - Proficiency in digital electronics design - Experience with VHDL, Verilog or SystemVerilog - Knowledge of system‑level modelling and verification - C++ programming competence - Python familiarity - Fluent written and spoken English - Willingness to learn French (nice‑to‑have)