Senior Analog IC Modelling Engineer

The Senior Analog IC Modelling Engineer will work at a semiconductor company in Lausanne, Switzerland, developing advanced high-performance technologies. The role involves creating and refining circuit models for high-frequency analog circuits, collaborating with analog designers and system modelling teams to ensure accurate and efficient models. The main responsibilities include developing models that support sub-block specifications and system requirements, verifying post-layout performance, and improving simulation efficiency. The engineer will also automate simulations, extract circuit performance, and document modelling results. Additionally, they will correlate modelling results with transistor-level simulations and present findings throughout the design process. The ideal candidate must have at least 7 years of experience in analog IC design and modelling, with a focus on high-frequency analog circuits. Proficiency in VerilogA, SystemVerilog, Python, or MATLAB, as well as experience with Cadence analog design tools, Ocean, and MDL, is required. What the role asks for: - 7+ years of analog IC design and modelling experience - Experience modelling high frequency analog circuits - Experience with VerilogA, SystemVerilog, Python or MATLAB - Experience with Cadence analog design tools - Experience with Ocean - Experience with MDL