Research Intern: Agentic System-Level Hardware Design

The role is a Research Intern focused on Agentic System-Level Hardware Design. Huawei, a global leader in information and communications technology (ICT) solutions, offers a range of products and solutions across various fields, including carrier networks, enterprise, consumer, and cloud computing. These solutions are deployed in over 170 countries, serving more than a third of the world's population. The main day-to-day responsibilities involve building and extending agentic engineering workflows. This includes carrying a hardware design from a structured, machine-checkable specification to a routed layout. The intern will apply these workflows to system-level designs such as RISC-V processors, vector units, accelerators, and SoCs. They will also evaluate the results at every stage using open-source tools like Verilator, Yosys, and OpenROAD. Additionally, the intern will develop verification methodologies to ensure the trustworthiness of the agents' results and read and analyze research papers to reproduce state-of-the-art results. The must-have requirements include being enrolled in or having completed a Master's or PhD program in Electrical Engineering, Computer Engineering, Computer Science, or a related field. A solid understanding of computer architecture and SoC design, including RISC-V processors, caches, memory systems, interconnects, and accelerators, is essential. Experience in RTL design using Verilog/SystemVerilog and Python, along with RTL simulation and digital implementation flows, is required. Proficiency in English is also necessary. Nice-to-have skills include experience with hardware construction languages or compiler-based flows, such as Chisel, Amaranth, or CIRCT/MLIR. Hands-on experience with LLMs, including agentic coding tools, tool use, context engineering, and evaluation of agent output, is also beneficial. The role is based in Zurich, Switzerland, within a multicultural team and a rapidly growing research laboratory focused on fundamental research in computing systems. What the role asks for: - Enrolled in or completed a Master's or PhD program in Electrical Engineering, Computer Engineering, Computer Science or a related field. - Solid understanding of computer architecture and SoC design. - Experience in RTL design (Verilog/SystemVerilog) and Python. - Experience in RTL simulation (e.g., Verilator) and digital implementation flows (e.g., Yosys, OpenROAD or commercial equivalents). - Proficiency in English. - Nice-to-have: Experience with hardware construction languages or compiler-based flows (e.g., Chisel, Amaranth, CIRCT/MLIR). - Nice-to-have: Hands-on experience building with LLMs (agentic coding tools, tool use, context engineering, evaluation of agent output).