Digital Design Engineer

Join an advanced semiconductor firm that is building the next‑generation, high‑bandwidth, low‑power AI interconnects. The company focuses on chiplet‑based connectivity and memory‑fabric solutions that move data over copper with a unique architecture. As a Digital Design Engineer you will create RTL and micro‑architecture for ultra‑fast digital blocks, design multi‑Gigabit serial links, DDR and memory interfaces, and implement PCIe, USB4 and other high‑speed protocols. You will define analog/digital interfaces together with mixed‑signal designers, run logic synthesis, static timing analysis, CDC checks and lint, and integrate IP at the chip level. The role also includes verification, design sign‑off and post‑silicon bring‑up, debugging and characterisation while collaborating closely with analog, verification and physical‑design teams. The ideal candidate brings 5–10 years of digital IC/ASIC design experience and holds an MSc or PhD in Electronics, Electrical Engineering, Communications or equivalent. You must be proficient in RTL design, SystemVerilog/Verilog, and familiar with ASIC design flows, high‑speed digital design and low‑power techniques. Experience with multi‑Gigabit transceivers, memory interfaces, mixed‑signal ICs, Python scripting or Cadence tools is considered a valuable plus. The position is based in Lausanne, Switzerland, offering the chance to work at the intersection of digital, mixed‑signal and high‑speed communications, turning system‑level concepts into production silicon that tackles AI hardware's biggest data‑movement challenges. What the role asks for: - 5–10 years digital IC/ASIC design experience - MSc/PhD in Electronics, Electrical Engineering or Communications - Strong RTL design expertise - SystemVerilog/Verilog proficiency - ASIC design‑flow experience - High‑speed digital design expertise - Low‑power design experience - Nice‑to‑have: Python scripting or Cadence tools