Firmware & FPGA Development Engineer (SY-BI-BP-2026-154-GRAP)

The SY‑BI group within CERN's Accelerator Systems Department designs and operates the instruments that monitor particle beams and assess their key parameters. As a Firmware & FPGA Development Engineer you will help create the next generation of beam‑position monitoring systems for CERN's injector complex, including the pre‑accelerators and the Antimatter Decelerator. The role sits at the crossroads of digital electronics, embedded systems, real‑time signal processing and accelerator physics, offering a hands‑on environment where innovative high‑speed data‑acquisition platforms based on fast digitisers and advanced System‑on‑Chip (SoC) technologies are built. Your daily work will involve developing, integrating and testing FPGA gateware together with embedded SoC firmware for a SoC device. You will implement data‑acquisition and processing logic as well as real‑time digital‑signal‑processing algorithms, then validate system performance both in the laboratory and in the accelerator environment. Data analysis will be carried out in Python, and you will support measurement campaigns across the accelerator complex. Collaboration is central: you will work alongside experienced engineers, physicists and technicians from various CERN teams. The position requires solid experience in digital signal processing and proven competence with FPGA and SoC development. You must be comfortable programming in Python and C++, and possess knowledge of Verilog, SystemVerilog, digital electronics and Python scripting. Fluency in spoken and written English is mandatory, together with a commitment to learn French. Applicants must be nationals of a CERN Member or Associate State, hold a background in Electronic Engineering (or a related field) and have either a Master's degree with 2‑6 years of post‑graduation experience or a PhD with no more than 3 years of post‑graduation experience. Candidates who have previously held a CERN fellow or graduate contract are not eligible. Experience with Xilinx Zynq UltraScale+ MPSoC or RFSoC is considered an advantage. The contract is fully onsite, 40 hours per week, for an initial 24 months with the possibility of extension to 36 months. The start date is 1 March 2027. Remuneration consists of a monthly net stipend of CHF 6 372 (Master's) or CHF 7 004 (PhD), 30 days of paid leave plus a two‑week annual closure, comprehensive health insurance, pension membership, family allowances and a relocation package where applicable. CERN also offers on‑the‑job and formal training, including language classes, within a diverse and inclusive community that pushes the frontiers of science. What the role asks for: - Experience in digital signal processing - Experience with FPGA and SoC development - Software programming in Python and C++ - Knowledge of Verilog and SystemVerilog - Knowledge of digital electronics - Fluent English; willing to learn French - CERN Member or Associate State national; Electronic Engineering background - Master's (2‑6 yr) or PhD (≤3 yr) experience; no prior CERN contract