Principal Analog IC Layout Engineer

IC Resources is looking for a Principal Analog/RF IC Layout Engineer to join a French client's team. The role centers on sophisticated analog and mixed‑signal chip design, demanding extensive custom layout proficiency. In this position you will partner with circuit designers to create and validate intricate analog and mixed‑signal IP. Tasks cover everything from initial floor‑plan creation, through integration of analog, mixed‑signal and ASIC blocks, to final verification steps such as design‑rule checks, layout‑versus‑schematic, electrical rule checks, extraction and design‑for‑manufacturing analysis. You will also synchronize layout timelines with fellow layout engineers and assess power‑grid routing, electromigration risks and signal‑coupling concerns. The candidate must bring roughly eight to ten years of experience in analog, mixed‑signal or RF layout. A solid grasp of high‑speed routing and parasitic behavior across various process nodes is required, as is hands‑on use of Cadence Virtuoso and the ability to read Calibre DRC, ERC and LVS reports. Knowledge of IR‑drop, RC delay, electromigration and chip‑finishing, plus proven floor‑planning and area‑estimation skills, are essential. Effective communication and close collaboration with designers are also mandatory. FinFET expertise would be a plus, while background in high‑speed BiCMOS layout is advantageous. The job can be performed from any location within France, provided the applicant already holds the legal right to work there, since sponsorship is not offered. What the role asks for: - 8–10 years analog, mixed‑signal or RF IC layout experience - Strong knowledge of high‑speed layout and parasitic effects - Proficiency with Cadence Virtuoso - Ability to interpret Calibre DRC, ERC and LVS results - Understanding of IR‑drop, RC delay and electromigration - Experience in floor planning and area estimation - Strong communication skills - FinFET experience (nice‑to‑have) - High‑speed BiCMOS layout experience (nice‑to‑have)